Location: Shanghai
Description
Intel DCG DEG is looking for FPGA talent for a new pioneering project. As a team, you will co-work with BIOS, SW and HW expertise and tightly engaged with customers. In this position, you will be responsible for understanding Intel provided IP blocks, delivering training to customers, troubleshooting issues and implementing new IP blocks.
Responsibilities for this position would involve but not be limited to:
1.Engage customer to understand customer’s need about IP or reference design
2.Work with team to define IP block and reference design architecture
3.Work with team to develop IP block/reference design and get it pass validation
4.Engage customer’s technical influencer to drive IP and reference design’s adoption
5.Build collateral and guide customer to use our IP block and reference design
6.Assist debugging with customer’s design and clarify issues when Intel IP blocks are used
7.Consolidate feedback to contribute to product definition
Qualifications
1.Must have a Masters or PhD in Computer Science, Computer Engineering, Electrical Engineering or related fields
2.Discipline, result orientation and ability to work in a dynamic team environment
3.Good English and Mandarin communication skills, both written and oral
4.Solid FPGA/ASIC design skill
Good RTL coding style to develop high performance/high efficiency/high reliability design
Deep understanding about timing closure to fix timing violation
Solid capability to understand algorithm and implement it with FPGA
Experience to develop test cases with good coverage
Additional Qualification and Experience would be a plus
1.Knowledge of CPU architecture, general GPU architecture, and network accelerators
2.Knowledge of heterogeneous (FPGA, CPU, GPGPU) hardware systems
3.Subject matter expertise in a particular class of algorithms, e.g. ML/DL, cryptography, compression, image & speech processing, packet processing, and etc.
4.Knowledge in latest design methodology like CUDA, OpenCL and HSA.